In microprocessor design, the ability to execute code in an efficient and timely manner directly impacts processor performance. In order to process instructions in a timely manner, the branch cache was developed. The branch cache has a plurality of memory locations for storing data regarding branch instructions used in user code, where user code is executed in the microprocessor to perform some function. The stored data in the branch cache is typically a branch address and a prediction of the branch result for each encountered branch. A two state model is typically used wherein a particular branch is either predicted as being taken or predicted as being not-taken depending upon a past history of the execution of the particular branch instruction. A branch instruction sends the flow of instruction execution in a microprocessor in one of two possible directions (i.e., if condition A goto address B else goto address C). If these two "arbitrary" directions B and C are not predicated ahead of branch execution by the processor, then the processor must cease pipeline operation after the branch instruction is entered into the pipeline until the branch's direction is determined (usually in the last stage of the pipeline execution unit). This discontinuation of pipeline processing reduces processor performance.
By using a branch cache, which predicts the direction of a branch accurately and correctly before the branch is executed, the microprocessor's pipeline execution unit(s) can continue to operate at full pipelined/full speed mode without having to cease pipelining for the branch. If the prediction of branch direction is correct most of the time, then performance improvements are gained due to the uninterrupted continuance of the pipelined mode. If prediction is incorrect most of the time, then performance may be hindered. Hindrance is due to the fact that the branch was predicted incorrectly resulting in the pipeline containing incorrect instructions from an incorrect branch path. The pipeline therefore must be flushed or "backed up" to remove those incorrect instructions and start pipelining in the correct execution direction dictated by the branch instruction.
A improved branch cache, wherein performance is further improved and branch prediction is more accurate, is needed.